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512k x 16 static ram cy62157cv30/33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05014 rev. *f revised august 31, 2006 features ? temperature ranges ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c ? voltage range: ? cy62157cv30: 2.7v?3.3v ? cy62157cv33: 3.0v?3.6v ? ultra-low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 5.5 ma @ f = f max ? low standby power ? easy memory expansion with ce 1 , ce 2 and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free 48 -ball fbga package functional description [1] the cy62157cv30/33 are high -performance cmos static rams organized as 512k words by 16 bits. these devices feature advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl?) in portable applications such as cellular telephones. the devices also have an aut omatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce 1 high or ce 2 low or both ble and bhe are high). the i nput/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low and ce 2 high and we low). writing to the device is accomplished by taking chip enable 1 (ce 1 ) and write enable (we ) inputs low and chip enable 2 (ce 2 ) high. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable 1 (ce 1 ) and output enable (oe ) low and chip enable 2 (ce 2 ) high while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the cy62157cv30/33 are available in a 48-ball fbga package. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 512k 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power -down circuit bhe ble ce 2 ce 1 ce 2 ce 1 [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 2 of 13 product portfolio product range v cc range power dissipation operating (i cc ) ma standby (i sb2 ) a f = 1 mhz f = f max min. typ. [2] max. typ. [2] max. typ. [2] max. typ. [2] max. cy62157cv30 automotive-e 2.7v 3.0v 3.3v 1.5 3 7 15 8 70 cy62157cv33 automotive-a 3.0v 3.3v 3.6v 1.5 3 5.5 12 10 30 automotive-e 1.5 3 7 15 10 80 pin configurations [2, 3, 4] fbga (top view) pin definitions name definition input a 0 -a 18 . address inputs input/output i/o 0 -i/o 15 . data lines. used as input or output lines depending on operation input/control we . write enable, active low. when selected low, a write is conducted. when selected high, a read is conducted. input/control ce 1 . chip enable 1, active low. input/control ce 2 . chip enable 2, active high. input/control oe . output enable, active low. controls the directi on of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins ground vss . ground for the device power supply vcc . power supply for the device notes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. 3. nc pins are not connected on the die. 4. e3 (dnu) can be left as nc or v ss to ensure proper application. we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 nc d e b a c f g h a 16 dnu v ss v cc 3 26 5 4 1 [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 3 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................. .............. .. ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ...?0.5v to v ccmax + 0.5v dc voltage applied to outputs in high-z state [5] ....................................?0.5v to v cc + 0.3v dc input voltage [5] .................................?0.5v to v cc + 0.3v output current into outputs (low) .............................20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current ................................................... > 200 ma operating range device range ambient temperature [t a ] [6] v cc cy62157cv30 automotive-e ?40c to +125c 2.7v ? 3.3v cy62157cv33 automotive-a ?40c to +85c 3.0v ? 3.6v automotive-e ?40c to +125c electrical characteristics over the operating range parameter description test conditions cy62157cv30-70 unit min. typ. [2] max. v oh output high voltage i oh = ?1.0 ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 v v ih input high voltage 2.2 v cc + 0.3v v v il input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?10 +10 a i oz output leakage current gnd < v o < v cc , output disabled ?10 +10 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v i out = 0 ma cmos levels 715ma f = 1 mhz 1.5 3 i sb1 automatic ce power-down current? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we , bhe and ble ) 870 a i sb2 automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.3v 870 a notes: 5. v il(min.) = ?2.0v for pulse durations less than 20 ns. 6. t a is the ?instant-on? case temperature. [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 4 of 13 electrical characteristics over the operating range parameter description test conditions cy62157cv33-70 unit min. typ. [2] max. v oh output high voltage i oh = ?1.0 ma v cc = 3.0v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 3.0v 0.4 v v ih input high voltage 2.2 v cc + 0.3v v v il input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc auto-a ?1 +1 a auto-e ?10 +10 a i oz output leakage current gnd < v o < v cc , output disabled auto-a ?1 +1 a auto-e ?10 +10 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v i out = 0 ma cmos levels auto-a 5.5 12 ma auto-e 7 15 f = 1 mhz auto-a/ auto-e 1.5 3 i sb1 automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f = 0 (oe ,we ,bhe ,and ble ) auto-a 10 30 a auto-e 10 80 a i sb2 automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v auto-a 10 30 a auto-e 10 80 a thermal resistance [7] parameter description test conditions fbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 c/w jc thermal resistance (junction to case) 16 c/w note: 7. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 5 of 13 capacitance [7] parameter description tes t conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 6pf c out output capacitance 8 pf ac test loads and waveforms v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns parameters 3.0v 3.3v unit r1 1.105 1.216 ? r2 1.550 1.374 ? r th 0.645 0.645 ? v th 1.75 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [2] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc = 1.5v, ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v auto-a 4 20 a auto-e 460 a t cdr [8] chip deselect to data retention time 0ns t r [8] operation recovery time t rc ns data retention waveform [9] notes: 8. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) >100 s. 9. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . v cc(min.) v cc(min.) t cdr v dr > 1.5 v data retention mode t r ce 1 or v cc bhe .ble ce 2 or [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 6 of 13 switching characteristics over the operating range [10] parameter description 70 ns unit min. max. read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low-z [11] 5ns t hzoe oe high to high-z [11, 12] 25 ns t lzce ce 1 low and ce 2 high to low-z [11] 10 ns t hzce ce 1 high or ce 2 low to high-z [11, 12] 25 ns t pu ce 1 low and ce 2 high to power-up 0 ns t pd ce 1 high or ce 2 low to power-down 70 ns t dbe bhe /ble low to data valid 70 ns t lzbe [11] bhe /ble low to low-z [13] 5ns t hzbe bhe /ble high to high-z [11, 12] 25 ns write cycle [14] t wc write cycle time 70 ns t sce ce 1 low and ce 2 high to write end 60 ns t aw address set-up to write end 60 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t bw bhe /ble pulse width 60 ns t sd data set-up to write end 30 ns t hd data hold from write end 0 ns t hzwe we low to high-z [11, 12] 25 ns t lzwe we high to low-z [11] 5ns notes: 10. test conditions assume signal transition time of 5 ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30-pf load capacitance. 11. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 12. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 13. when both byte enables are toggled together this value is 10 ns. 14. the internal write time of the me mory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going in active. the data input set-up and hold timing should be referen ced to the edge of the signal that terminates the write. [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 7 of 13 switching waveforms read cycle no. 1 (address transition controlled) [15, 16] read cycle no. 2 (oe controlled) [16, 17] notes: 15. device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , ce 2 = v ih . 16. we is high for read cycle. 17. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current bhe /ble t lzbe t hzbe [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 8 of 13 write cycle no. 1 (we controlled) [14, 18, 19] notes: 18. data i/o is high-impedance if oe = v ih . 19. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high-impedance state. 20. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 20 bhe /ble t bw [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 9 of 13 write cycle no. 2 (ce 1 or ce 2 controlled) [14, 18, 19] write cycle no. 3 (we controlled, oe low) [19] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 20 bhe /ble t bw t sa data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o note 20 t bw bhe /ble [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 10 of 13 write cycle no. 4 (bhe /ble controlled, oe low) [19] truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o o ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h h l l high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o o ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) switching waveforms (continued) data i/o address t hd t sd t sa t ha t aw t wc ce 1 we data in valid note 20 t bw bhe /ble t sce ce 2 t pwe [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 11 of 13 typical dc and ac characteristics 12.0 10.0 6.0 4.0 0 8.0 i sb ( a) 12.0 10.0 6.0 4.0 2.0 2.2 0.0 8.0 i cc (ma) supply voltage (v) supply voltage (v) mobl mobl 2.2 2.0 (f = 1 mhz) (f = f max , 70ns) 14.0 2.5 2.7 2.5 2.7 12.0 10.0 6.0 4.0 2.0 2.7 3.3 0.0 8.0 i cc (ma) supply voltage (v) mobl (f = 1 mhz) (f = f max , 70ns) 14.0 3.0 12.0 10.0 6.0 4.0 2.0 3.0 3.6 0.0 8.0 i cc (ma) supply voltage (v) 14.0 3.3 mobl 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) supply voltage (v) 3.6 2.0 3.3 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) standby current vs. supply voltage supply voltage (v) mobl 2.0 2.7 3.3 50 30 20 10 3.0 3.6 supply voltage (v) 0 40 t aa (ns) 60 3.3 50 30 20 10 2.2 supply voltage (v) 0 40 t aa (ns) 60 2.5 2.7 50 30 20 10 supply voltage (v) access time vs. supply voltage 0 40 t aa (ns) 60 3.0 2.7 3.3 mobl operating current vs. supply voltage mobl mobl mobl (f = f max , 70ns) (f = 1 mhz) [2] [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 12 of 13 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram mobl, mobl2, and more battery life are trademarks of cypr ess semiconductor corporation. all product and company names mentioned in this document may be the tr ademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 70 cy62157cv30ll-70bae 51-85128 48-ball (6 mm x 10 mm x 1.2 mm) fbga automotive-e cy62157cv33ll-70baxa automotive-a CY62157CV33LL-70BAE automotive-e a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 10.000.10 a 10.000.10 6.000.10 b 1.875 2.625 0.36 48-ball (6 mm x 10 mm x 1.2 mm) fbga (51-85128) 51-85128-*d [+] feedback [+] feedback
cy62157cv30/33 document #: 38-05014 rev. *f page 13 of 13 document history page document title: cy62157cv30/33 512k x 16 static ram document number: 38-05014 rev. ecn no. issue date orig. of change description of change ** 106184 05/10/01 hrt/mgn new data sheet ? advance information *a 107241 07/24/01 mgn made corrections to advance information added 55 ns bin *b 109621 03/11/02 mgn changed from advance information to final *c 114218 05/01/02 gug/mgn improved typical and max i cc values *d 238448 see ecn aju added automotive product information *e 269729 see ecn syt added automotive product information for cy62157cv30 ? 70 ns added i ix and i oz values for automotive range of cy62157cv33 ? 70 ns *f 498575 see ecn nxr removed industrial operating range removed 55 ns speed bin removed cy62157cv25 part number from the product offering added automotive-a operating range updated the ordering information table [+] feedback [+] feedback

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